The present invention relates to tape substrate-based semiconductor packages, and more particularly to an improved tape substrate design that reduces warpage.
Integrated circuits are typically packaged before they are used with other components as part of a larger electronic system. Most packages are constructed with die mounted on a substrate with bond pads on the die connected to conductive lines or traces on the surface. These substrates may be tape, ceramic, or printed circuit board laminate.
Tape substrates are very thin and are used for CSP (Chip Size Packages) and BGA (Ball Grid Arrays) semiconductor packages, which are ideal for cellular phones, and other such devices. Use of durable polyimide film makes extremely fine patterning possible, increasing circuit density.
Although tape substrates offer advantages over other types of packages, the materials comprising the package and the thinness of tape substrates create a problem when used for semiconductor packaging. The construction of a tape substrate-based package typically includes three different types of materials, namely, a substrate comprising kapton or polyimide film, copper circuits having a plating of nickel/gold, and a solder mask. Each of these different materials have different coefficients of thermal expansion, and in this case, the solder mask expansion coefficient is more dominant than the others. This difference in expansion coefficient rates induces warpage of the semiconductor package during and after assembly, resulting in die cracks. Also, when used in BGA packages, the warpage results in loss of ball coplanarity.
A current solution toward solving this problem is the use of rigid substrates, which comprise Bismaleimidie Trizine (BT) or FR5. Although rigid substrates do not suffer a problem of warpage, routing density is poor with rigid substrates and overall thickness of the package is higher. Therefore, for some packaging applications, the use of rigid substrate is not a viable option.
Accordingly, what is needed is an improved tape substrate design that reduces warpage, but does not increase the overall thickness of the package. The present invention addresses such a need.
The present invention provides an improved tape substrate design for a semiconductor package. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention, an extra metal layer is added to the circuitry to increase rigidity of the tape substrate. In a preferred embodiment, the metal layer is added at the die pads, between the die pads and vias, and between the metal traces.
According to the system and method disclosed herein, the extra metal layer reduces warpage of the tape substrate package, which both minimizes die cracks and enhances coplanarity of balls in BGA packages. Furthermore, the extra metal layer does not increase the thickness of the tape substrate package.